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-- Project Name:	 Stepper Motor Driver
-- Class: 			 M.Tech ELDT, 2nd Semester
-- Name: 			 Sujit Kr Nayak
-- Roll N0: 		 ELD09006
-- Create Date:    15:31:50 04/20/2010 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Stepper_Driver is
generic(N:positive:=8);
    Port ( clk,rs,stsp : in  STD_LOGIC;
           --dir : in  STD_LOGIC;
			  clk_div : buffer STD_LOGIC;
           z : out  STD_LOGIC_VECTOR (3 downto 0));
end Stepper_Driver;

architecture Behavioral of Stepper_Driver is



begin

divide_clock: process (rs,clk)							  
		
		variable cnt: NATURAL;
		begin
		  	if rs='0' then
		  		cnt:=0;
				clk_div<='0';
				elsif clk'event and clk ='1' then
				cnt:= cnt+1;
					if cnt =N then
					clk_div <= not clk_div;
					cnt:=0;
				end if;
			end if;
	end process divide_clock;        

drive: process (clk_div,stsp)							  
		
		variable cn: std_logic_vector (1 downto 0);
		begin
		  	if stsp='0' then
		  		cn :="00";
				--clk_div<='0';
				elsif clk_div'event and clk_div ='1' then
				cn:= cn+1;
					if cn > "11" then
					cn:="00";
				end if;
			end if;
			
			case cn is
			when "00"=> z<= X"8";
			when "01"=> z<= X"4";
			when "10"=> z<= X"2";
			when others => z<=X"1";
			end case;
	end process drive;

	
end Behavioral;