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-- Project Name:	 Second Counter with Start Stop and Reset
-- Class: 			 M.Tech ELDT, 2nd Semester
-- Name: 			 Sujit Kr Nayak
-- Roll N0: 		 ELD09006
-- Create Date:    02:36:31 04/10/2010 
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Seven_Seg_Sec_Ctr is
    Port (s : out  STD_LOGIC_VECTOR (6 downto 0);
			 en1,en2, led: out STD_LOGIC;
			 clk,rst,st_sp: in STD_LOGIC); 
			
end Seven_Seg_Sec_Ctr;

architecture Behavioral of Seven_Seg_Sec_Ctr is


signal d: STD_LOGIC_VECTOR (3 downto 0);
signal cntr1 : std_logic_vector(3 downto 0):="0000";
signal cntr2 : std_logic_vector(3 downto 0):="0000";
signal clkctr: std_logic_vector(23 downto 0):=X"000000";
signal oneHz: std_logic;

begin

--------------------------- Clock Divider---------------------------
 divide_clock: process (clk)							  
		begin
		  	if rising_edge(clk) then
		  		if clkctr= X"1E847F" then		-- Dividing by 1999999 to get 1Hz from 4 MHz
					oneHz <=not oneHz; 			-- Switch the level oneHz is the 1 Hz pulse
					clkctr<=X"000000";
				else
					clkctr<=clkctr+X"000001";
				end if;
			end if;
	end process divide_clock;  
---------------------------------------------------------------------	


-------------------------- Second Counter Block----------------------
counter:process (oneHz,rst,st_sp)
		begin
		led <= oneHz;
			if st_sp='1' and oneHz = '1' and oneHz'Event then
				if cntr1 = "1001"or rst='1' then								--if one second counter reaches 9 reset to 0
				   cntr1 <= "0000";			
					if cntr2 = "1001" or rst='1' then							--if ten second counter reaches 5 reset to 0
						cntr2 <= "0000";
					else
						cntr2 <= cntr2 + 1;	
					end if;
				else
					cntr1 <= cntr1 + 1;
				end if;
			end if;
	end process counter;

-------------------------------------------------------------------------



--------------------------------- Display Block -------------------------
process (cntr1,cntr2,clkctr(8))
begin 

			en1 <= clkctr(8);										--display switching
			en2 <= not(clkctr(8));
			case clkctr(8) is
				when '1' =>											
					d <= cntr2;								
					
				when others =>
					d <= cntr1;
										
			end case;
			
			
	------------- BCD to Seven segment Conversion reduced by K-Map  --------

	-- segment a
	s(0) <=    ((NOT d(3)) AND (NOT d(2)) AND (NOT d(1)) AND (d(0))) 
			OR ((NOT d(3)) AND (d(2)) AND (NOT d(1)) AND (NOT d(0))) 
			OR ((d(3)) AND (d(2)) AND (NOT d(1)) AND (d(0))) 
			OR ((d(3)) AND (NOT d(2)) AND (d(1)) AND (d(0)));
	-- segment b
	s(1) <=    ((NOT d(3)) AND (d(2)) AND (NOT d(1)) AND (d(0))) 
			OR ((d(2)) AND (d(1)) AND (NOT d(0))) 
			OR ((d(3)) AND (d(2)) AND (NOT d(0))) 
			OR ((d(3)) AND (d(1)) AND (d(0)));
	-- segment c
	s(2) <=    ((NOT d(3)) AND (NOT d(2)) AND (d(1)) AND (NOT d(0))) 
			OR ((d(3)) AND (d(2)) AND (NOT d(0))) 
			OR ((d(3)) AND (d(2)) AND (d(1)));
	-- segment d
	s(3) <=    ((NOT d(3)) AND (d(2)) AND (NOT d(1)) AND (NOT d(0))) 
			OR ((NOT d(2)) AND (NOT d(1)) AND (d(0))) 
			OR ((d(2)) AND (d(1)) AND (d(0))) 
			OR ((d(3)) AND (NOT d(2)) AND (d(1)) AND (NOT d(0)));
	-- segment e
	s(4) <=    ((NOT d(3)) AND (d(2)) AND (NOT d(1))) 
			OR ((NOT d(2)) AND (NOT d(1)) AND (d(0))) 
			OR ((NOT d(3)) AND (d(0))); 
	-- segment f
	s(5) <=    ((NOT d(3)) AND (NOT d(2)) AND (d(0))) 
			OR ((NOT d(3)) AND (NOT d(2)) AND (d(1))) 
			OR ((NOT d(3)) AND (d(1)) AND (d(0))) 
			OR ((d(3)) AND (d(2)) AND (NOT d(1)) AND (d(0)));
	-- segment g
	s(6) <=    ((NOT d(3)) AND (NOT d(2)) AND (NOT d(1))) 
			OR ((NOT d(3)) AND (d(2)) AND (d(1)) AND (d(0))) 
			OR ((d(3)) AND (d(2)) AND (NOT d(1)) AND (NOT d(0))) ;
end process;
end Behavioral;





----------------------------  By: Sujit, Ajay and Sushanta  -------------------------