----------------------------------------------------------------------------------
-- Company: www.sanuzrworld.co.nr
-- Engineer: Sujit Kr Nayak
-- 
-- Create Date:    16:31:15 03/02/2010 
-- Design Name: 
-- Module Name:    mux8_1 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Mux_8_1 is
    Port ( p,q,r,s,t,u,v,w : in  STD_LOGIC;
           s1,s2,s3 : in  STD_LOGIC;
           z : out  STD_LOGIC);
end Mux_8_1;

architecture Behavioral of Mux_8_1 is
signal z1,z2,z3:std_logic;
component Mux_4_1 is
port(a,b,c,d,en,sel1,sel2:in STD_LOGIC;z:out std_logic);
end component;
begin
f1:Mux_4_1 port map(p,q,r,s,s3,s1,s2,z1);
z3<=not s3;
f2:Mux_4_1 port map(t,u,v,w,z3,s1,s2,z2);
z<=z1 or z2;
end Behavioral;