---------------------------------------------------------------------------------- -- Company: www.sanuzrworld.co.nr -- Engineer: Sujit Kr Nayak -- -- Create Date: 15:54:10 03/02/2010 -- Design Name: -- Module Name: mux4_1 - Behavioral -- Project Name: multiplexor 4:1 -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Mux_4_1 is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; d : in STD_LOGIC; en : in STD_LOGIC; s0,s1:in STD_LOGIC; z : out STD_LOGIC); end Mux_4_1; architecture Behavioral of Mux_4_1 is begin process(en,s0,s1) variable x:std_logic; begin if en='1' then if (s0='0' and s1='0')then x:=a; elsif (s0='0' and s1='1')then x:=b; elsif (s0='1' and s1='0')then x:=c; else x:=d; end if; end if; z<=x; end process; end behavioral;