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-- Company: www.sanuzrworld.co.nr
-- Engineer: Sujit Kr Nayak
-- 
-- Create Date:    11:24:08 03/05/2010 
-- Design Name: 
-- Module Name:    gray2bin - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Gray_Binary is
    Port ( g0,g1,g2,g3 : in  STD_LOGIC;
           b0,b1,b2,b3 : inout  STD_LOGIC);
end Gray_Binary;

architecture Behavioral of Gray_Binary is

begin
b3<=g3;
b2<=b3 xor g2;
b1<=b2 xor g1;
b0<=b1 xor g0;


end Behavioral;