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-- Company: www.sanuzrworld.co.nr
-- Engineer: Sujit Kr Nayak
-- 
-- Create Date:    15:21:54 03/03/2010 
-- Design Name: 
-- Module Name:    adder_8 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity FullAdder_8 is
    Port ( D,E : in  STD_LOGIC_VECTOR (7 downto 0);
           Cin1 : in  STD_LOGIC;
           Sum : out  STD_LOGIC_VECTOR (7 downto 0);
           Cout1 : out  STD_LOGIC);
end FullAdder_8;

architecture Behavioral of FullAdder_8 is
component F_A is
Port ( p : in  STD_LOGIC; q : in  STD_LOGIC;
           cin : in  STD_LOGIC;
           sum : out  STD_LOGIC;
           cout : out  STD_LOGIC);
end component;
signal c0,c1,c2,c3,c4,c5,c6:std_logic;                                                                                                                                                                          
begin
a1:F_A port map(D(0),E(0),Cin1,Sum(0),c0);
a2:F_A port map(D(1),E(1),c0,Sum(1),c1);
a3:F_A port map(D(2),E(2),c1,Sum(2),c2);
a4:F_A port map(D(3),E(3),c2,Sum(3),c3);
a5:F_A port map(D(4),E(4),c3,Sum(4),c4);
a6:F_A port map(D(5),E(5),c4,Sum(5),c5);
a7:F_A port map(D(6),E(6),c5,Sum(6),c6);
a8:F_A port map(D(7),E(7),c6,Sum(7),Cout1);

end Behavioral;