---------------------------------------------------------------------------------- -- Project Name: Frequency Counter - 2 -- Class: M.Tech ELDT, 2nd Semester -- Name: Sujit Kr Nayak -- Roll N0: ELD09006 -- Create Date: 12:50:26 04/28/2010 ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Freqn_Ctr is ---------------------------------------------- generic (frck: INTEGER := 5; --clock freq. fxmax: INTEGER := 15); --maximum freqn port (clk, un_clk: in BIT; int_out: out BIT; leds_out: out INTEGER RANGE 0 to fxmax); end Freqn_Ctr; ---------------------------------------------- architecture behavioral of Freqn_Ctr is signal tinterval: BIT; signal temp: INTEGER RANGE 0 to fxmax; begin ----- Time window: ------------------------ process (clk) variable cnt: INTEGER RANGE 0 to frck; begin if (clk'EVENT and clk='1') then cnt := cnt + 1; if (cnt=frck) then tinterval <= '1'; elsif (cnt=frck+1) then tinterval <= '0'; cnt := 0; end if; end if; end process; ------ Counter for unknown clock frequency: --------------------- process (un_clk, tinterval) variable cntr: INTEGER RANGE 0 to 20; begin if (tinterval='1') then cntr := 0; elsif (un_clk'EVENT and un_clk='1') then cntr := cntr + 1; end if; temp <= cntr; end process; -------- Register: ------------------------- process (tinterval) begin if (tinterval'EVENT and tinterval='1') then leds_out <= temp; end if; end process; int_out <= tinterval; end Behavioral;