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-- Project Name:	 Frequency_Counter-1
-- Class: 			 M.Tech ELDT, 2nd Semester
-- Name: 			 Sujit Kr Nayak
-- Roll N0: 		 ELD09006
-- Create Date:    12:50:26 04/28/2010 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;


entity Freq_ctr is
    Port (s : out  STD_LOGIC_VECTOR (6 downto 0);
			 en1,en2, led: out STD_LOGIC;
			 clk,freq_clk: in STD_LOGIC); 
			
end Freq_ctr;

architecture Behavioral of Freq_ctr is


signal d: STD_LOGIC_VECTOR (3 downto 0);
signal cntr1 : std_logic_vector(3 downto 0):="0000";
signal cntr2 : std_logic_vector(3 downto 0):="0000";
signal clkctr: std_logic_vector(23 downto 0):=X"000000";
signal oneHz: std_logic;

begin


 divide_clock: process (clk)							  
		begin
		  	if rising_edge(clk) then
		  		if clkctr= X"1E847F" then								--
					oneHz <=not oneHz; 								-- Switch the level
					clkctr<=X"000000";
					
				else
					clkctr<=clkctr+X"000001";
				end if;
			end if;
	end process divide_clock;
	
led <= oneHz;



counter:process (freq_clk, oneHz)
		begin
		if oneHz='1' then
			if freq_clk = '1' and freq_clk'Event then
				if cntr1 = "1001" then								--if one second counter reaches 9 reset to 0
				   cntr1 <= "0000";			
					if cntr2 = "1001" then							--if ten second counter reaches 5 reset to 0
						cntr2 <= "0000";
					else
						cntr2 <= cntr2 + 1;	
					end if;
				else
					cntr1 <= cntr1 + 1;
				end if;
			end if;
		end if;
	end process counter;
	





process (cntr1,cntr2,clkctr(8))
begin 

			en1 <= clkctr(8);										--display switching
			en2 <= not(clkctr(8));
			case clkctr(8) is
				when '1' =>											
					d <= cntr2;								
					
				when others =>
					d <= cntr1;
										
			end case;

	-- segment a
	s(0) <=    ((NOT d(3)) AND (NOT d(2)) AND (NOT d(1)) AND (d(0))) 
			OR ((NOT d(3)) AND (d(2)) AND (NOT d(1)) AND (NOT d(0))) 
			OR ((d(3)) AND (d(2)) AND (NOT d(1)) AND (d(0))) 
			OR ((d(3)) AND (NOT d(2)) AND (d(1)) AND (d(0)));
	-- segment b
	s(1) <=    ((NOT d(3)) AND (d(2)) AND (NOT d(1)) AND (d(0))) 
			OR ((d(2)) AND (d(1)) AND (NOT d(0))) 
			OR ((d(3)) AND (d(2)) AND (NOT d(0))) 
			OR ((d(3)) AND (d(1)) AND (d(0)));
	-- segment c
	s(2) <=    ((NOT d(3)) AND (NOT d(2)) AND (d(1)) AND (NOT d(0))) 
			OR ((d(3)) AND (d(2)) AND (NOT d(0))) 
			OR ((d(3)) AND (d(2)) AND (d(1)));
	-- segment d
	s(3) <=    ((NOT d(3)) AND (d(2)) AND (NOT d(1)) AND (NOT d(0))) 
			OR ((NOT d(2)) AND (NOT d(1)) AND (d(0))) 
			OR ((d(2)) AND (d(1)) AND (d(0))) 
			OR ((d(3)) AND (NOT d(2)) AND (d(1)) AND (NOT d(0)));
	-- segment e
	s(4) <=    ((NOT d(3)) AND (d(2)) AND (NOT d(1))) 
			OR ((NOT d(2)) AND (NOT d(1)) AND (d(0))) 
			OR ((NOT d(3)) AND (d(0))); 
	-- segment f
	s(5) <=    ((NOT d(3)) AND (NOT d(2)) AND (d(0))) 
			OR ((NOT d(3)) AND (NOT d(2)) AND (d(1))) 
			OR ((NOT d(3)) AND (d(1)) AND (d(0))) 
			OR ((d(3)) AND (d(2)) AND (NOT d(1)) AND (d(0)));
	-- segment g
	s(6) <=    ((NOT d(3)) AND (NOT d(2)) AND (NOT d(1))) 
			OR ((NOT d(3)) AND (d(2)) AND (d(1)) AND (d(0))) 
			OR ((d(3)) AND (d(2)) AND (NOT d(1)) AND (NOT d(0))) ;
end process;
end Behavioral;