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-- Company: www.sanuzrworld.co.nr
-- Engineer:  Sujit Kumar Nayak
-- 
-- Create Date:    09:57:22 03/03/2010 
-- Design Name: 
-- Module Name:    fulladder - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity F_A is
    Port ( p : in  STD_LOGIC;
           q : in  STD_LOGIC;
           cin : in  STD_LOGIC;
           sum : out  STD_LOGIC;
           cout : out  STD_LOGIC);
end F_A;

architecture Behavioral of F_A is
component H_A is
port(a,b:in std_logic;sum,carry:out std_logic);
end component;
signal s1,c1,c2:std_logic;
begin
x1:H_A port map(p,q,s1,c1);
x2:H_A port map(s1,cin,sum,c2);
cout<=c1 or c2;
end Behavioral;