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-- Company: www.sanuzrworld.co.nr
-- Engineer:  Sujit Kumar Nayak

-- 
-- Create Date:    15:40:38 03/02/2010 
-- Design Name: 
-- Module Name:    dec_3_8_beh - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity DEC_3_8_BEH is
    Port ( A : in  STD_LOGIC;
          B : in  STD_LOGIC;
           C,En : in  STD_LOGIC;
           Z : out  STD_LOGIC_VECTOR (7 downto 0));
end DEC_3_8_BEH;

architecture Behavioral of DEC_3_8_BEH is

begin
process(En)
variable ABAR,BBAR,CBAR:std_logic;
begin
ABAR:=not A;
BBAR:=not B;
CBAR:=not C;
if En='1' then
Z(0)<=ABAR and BBAR and CBAR;
Z(1)<=ABAR and BBAR and C;
Z(2)<=ABAR and B and CBAR;
Z(3)<=ABAR and B and C;
Z(4)<=A and BBAR and CBAR;
Z(5)<=A and BBAR and C;
Z(6)<=A and B and CBAR;
Z(7)<=A and B and C;
else
Z<="11111111";
end if;
end process;
end Behavioral;