----------------------------------------------------------------------------------
-- Company: www.sanuzrworld.co.nr
-- Engineer:  Sujit Kumar Nayak
-- 
-- Create Date:    16:53:43 03/03/2010 
-- Design Name: 
-- Module Name:    bin_to_gray - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Binary_Gray is
    Port ( b : inout  STD_LOGIC_VECTOR (3 downto 0);
           g : inout  STD_LOGIC_VECTOR (3 downto 0));
end Binary_Gray;

architecture dataflow of Binary_Gray is

begin
g(3)<=b(3);
g(2)<=g(3) xor b(2);
g(1)<=g(2) xor b(1);
g(0)<=g(1) xor b(0);

end dataflow;