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-- Company: www.sanuzrworld.co.nr
-- Engineer: Sujit Kumar Nayak
-- 
-- Create Date:    11:59:38 03/05/2010 
-- Design Name: 
-- Module Name:    and_gate - Behavioral 
-- Project Name: AND Generic
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity AND_Generic is
generic(n:natural:=8);
    Port ( a : in  STD_LOGIC_VECTOR (9 downto 0);
           z : out  STD_LOGIC);
end AND_Generic;

architecture generic_str of AND_Generic is

begin
process(a)
variable x:std_logic;
begin
x:='1';
for k in 1 to n loop
x:=x and a(k);
exit when x='0';
end loop;
z<=x;
end process;
end generic_str;