----------------------------------------------------------------------------------
-- Project Name:	 ADC Interfacing and Displaying Name
-- Class: 			 M.Tech ELDT, 2nd Semester
-- Name: 			 Sujit Kr Nayak
-- Roll N0: 		 ELD09006
-- Create Date:    12:50:26 04/28/2010 
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ADC_Interface is
    Port ( clk,rst,eoc : in  STD_LOGIC;
           data : in  STD_LOGIC_VECTOR (7 downto 0);
           soc,ale,oe,adcclk : out  STD_LOGIC;
           address : out  STD_LOGIC_VECTOR (2 downto 0);
           adc_out : out  STD_LOGIC_VECTOR (7 downto 0));
end ADC_Interface;

architecture Behavioral of ADC_Interface is
signal sig_adcclk : STD_LOGIC;
signal count : STD_LOGIC_VECTOR(7 downto 0);

begin
address <= "111";
process(clk,rst)
begin
if (rst = '1') then
     count <= (others => '0');
	  sig_adcclk<='0';
	  elsif (clk'event and clk='1') then
	  count<=count+'1';
	  if (count="11111111")then
	  sig_adcclk<= not sig_adcclk;
	 end if;
	 end if;
	end process;
adcclk <= sig_adcclk;

process(sig_adcclk, rst)
variable temp: std_logic_vector(3 down to 0);
variable flag : std_logic;
begin

if (rst='1') then

	oe<='0';
	soc<='0';
	ale<='0';
	temp<="0000";
	adc_out<=(others=>'1');
	flag:= '1';
elsif rising_edge (sig_adcclk)then
	if (flag='1') then
	temp:= temp+1;
		if (temp="0010")then
			ale<='0';
			soc<='1';
		elsif (temp<"1001")then
			ale<='0';
			soc<='0';
		elsif (temp="1011") then
			oe<='1';
		elsif (temp<"1101")then
			adc_out<= data;
		elsif (temp<"1111")then
			oe<='0';
			flag:='0';
			temp:= "0000";
		end if;
	end if;
end if;
end process;
	  
end Behavioral;